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Silicon Labs /EFR32MG22C224F512IM32 /CRYPTOACC_NS_RNGCTRL /CLKDIV

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Interpret as CLKDIV

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0VALUE

Description

Sample clock divider. The frequency at which the outputs of the rings are sampled is given by Fs = Fpclk/(ClkDiv + 1)

Fields

VALUE

Sample clock divider

Links

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data